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general description the max5048c is a high-speed mosfet driver capable of sinking/sourcing 7a/3a peak currents. this device takes logic input signals and drives a large external mosfet. the device has inverting and noninverting inputs that give the user greater flexibility in controlling the mosfet. the device also has the features necessary to drive low-side enhancement-mode gallium nitride (gan) fets. the device features two separate outputs working in complementary mode, offering flexibility in controlling both turn-on and turn-off switching speeds. the device has internal logic circuitry, which prevents shoot-through during output state changes. the logic inputs are protected against voltage spikes up to +14v, regardless of v+ voltage. propagation delay time is minimized and matched between the inverting and noninverting inputs. the device has very fast switching times combined with very short propagation delays (8ns, typ) making it ideal for high-frequency circuits. the device operates from a +4v to +14v single power supply, typically consuming 0.5ma of supply current and has ttl input logic levels. this device is available in a 6-pin sot23 package and provides an upgrade path for users of the max5048b. applications power mosfet switching switch-mode power supplies dc-dc converters motor control power-supply modules benefts and features improved power conversion efficiency ? low 8ns propagation delay ? 5ns typical rise and 4ns typical fall times with 1nf load ? 0.3 open-drain n-channel sink output ? 0.84 open-drain p-channel source output improved emi ? independent source/sink outputs for controllable rise and fall times reduced solution size and cost ? low input capacitance (10pf, typ) ? 6-pin sot-23 package ? +4v to +14v single power supply greater flexibility in controlling the mosfet ? matching delay time between inverting and noninverting inputs ? 7a/3a peak sink/source drive current ? ttl logic-level inputs with hysteresis for noise immunity improved system reliabilty ? inputs rated to +14v regardless of v+ voltage ? thermal shutdown protection ? -40c to +125c operating temperature range easy upgrade from max5048b ? pin-compatible with the max5048b 19-6451; rev 1; 1/15 ordering information appears at end of data sheet. typical operating circuit evaluation kit available p_out v+ max5048c in+ n in- gnd n_out v+ max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver
maxim integrated 2 electrical characteristics (v+ = 12v, c l = 0, t a = -40c to +125c, unless otherwise noted. typical values are specified at t a = +25c.) (note 2) note 1: measured on the max5048c evaluation kit. v+, in+, in-, p_out, n_out to gnd .................. -0.3v to +16v operating temperature range ......................... -40c to +125c storage temperature range ............................ -65c to +150c junction temperature ...................................................... +150c lead temperature (soldering, 10s) ................................. +300c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) junction-to-ambient thermal resistance ( ja ) .............. 80c/w absolute maximum ratings parameter symbol conditions min typ max units power supply (v+) v+ operating range v+ 4 14 v v+ undervoltage lockout uvlo v+ rising 3.28 3.45 3.63 v v+ uvlo hysteresis 200 mv v+ uvlo to output delay v+ rising, in+ = v+, in- = gnd 127 s v+ supply current i+ q not switching, v+ = 14v 0.5 1 ma i+ sw v+ = 6 v, switching at 1mhz 2.65 n-channel output driver output resistance pulling down r on-n v+ = 14v, i n_out = -100ma 0.31 0.55 ? v+ = 4.5v, i n_out = -100ma 0.32 0.56 power-off pulldown resistance v+ = unconnected, i n_out = -10ma, t a = +25 n c 4 6.1 8.5 ? power-off pulldown clamp voltage v+ = unconnected, i n_out = -10ma, t a = +25 n c 0.95 1.29 1.65 v output leakage current i lk-n n_out = 14v 6.5 11 a peak output current (sinking) i pk-n c l = 10 nf 7 a p-channel output driver output resistance pulling up r on-p v+ = 14v, i p_out = 100ma 0.84 1.47 ? v+ = 4.5v, i p_out = 100ma 0.88 1.55 output leakage current i lk-p p_out = 0v -1 +1 a peak output current (sourcing) i pk-p c l = 10nf 3 a logic input (in+, in-) logic high input voltage v ih 2.0 v logic low input voltage v il 0.8 v logic input hysteresis v hys 300 mv logic input current in+ = in- = v+ or 0v, v+ = 14v -1000 +1000 na logic input capacitance c in (note 3) 10 pf max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
maxim integrated 3 electrical characteristics (continued) (v+ = 12v, c l = 0, t a = -40c to +125c, unless otherwise noted. typical values are specified at t a = +25c.) (note 2) note 2: all devices are production tested at t a = +25c. limits over temperature are guaranteed by design. note 3: design guaranteed by bench characterization. limits are not production tested. switching characteristics (v+ = 14v) (figure 2 and note 3) rise time t r c l = 1nf 5 ns c l = 4.7nf 19 c l = 10nf 37 fall time t f c l = 1nf 4 ns c l = 4.7nf 10 c l = 10nf 18 turn-on delay time t d-on c l = 1nf 3 7 18 ns turn-off delay time t d-off c l = 1nf 3 7 18 ns break-before-make time 5 ns switching characteristics (v+ = 4.5v) (figure 2 and note 3) rise time t r c l = 1nf 4 ns c l = 4.7nf 13 c l = 10nf 28 fall time t f c l = 1nf 4 ns c l = 4.7nf 7 c l = 10nf 13 turn-on delay time t d-on c l = 1nf 2 8 21 ns turn-off delay time t d-off c l = 1nf 2 8 21 ns break-before-make time 5 ns thermal shutdown thermal shutdown threshold temperature rising 166 o c thermal shutdown hysteresis 13 o c max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
maxim integrated 4 typical operating characteristics (c l = 1nf, t a = +25c, unless otherwise noted.) rise time vs. supply voltag e max5048c toc01 supply voltage, v+ (v) rise time (ns) 12 10 8 6 2.5 3.0 3.5 4.0 2.0 41 4 t a = +125c t a = +85c t a = 0c t a = -40c t a = +25c fall time vs. supply voltage max5048c toc02 supply voltage, v+ (v) fall time (ns) 10 12 8 6 2.0 2.5 3.0 1.5 41 4 t a = +125c t a = +85c t a = 0c t a = -40c t a = +25c propagation delay time (low to high) vs. supply voltag e max5048c toc03 supply voltage, v+ (v) propagation delay time (ns) 12 10 8 6 10 12 14 16 18 8 41 4 t a = +125c t a = +85c t a = 0c t a = -40c t a = +25c propagation delay tim e (high to low) vs. supply voltag e max5048c toc04 supply voltage, v+ (v) propagation delay (ns) 12 10 8 6 10 12 14 16 18 8 41 4 t a = +125c t a = +85c t a = 0c t a = -40c t a = +25c supply voltage, v+ (v) supply current (ma) 12 10 8 6 0.5 1.0 1.5 2.0 2.5 3.0 0 41 4 supply current vs. supply voltage (c l = 0nf) max5048c toc05 1mhz 500khz 100khz 75khz 40khz supply currrent vs. load capacitance (v+ = 10v, f =100khz) max5048c toc06 load capacitance (nf) supply current (ma) 2000 1500 1000 500 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 02 500 supply current vs. temperature (v+ = 10v, c l = 0nf, f = 100khz) max5048c toc07 ambient temperature (c ) supply current (ma) 100 80 60 40 20 0 -20 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.50 -40 120 supply voltage, v+ (v) input threshold voltage (v) 12 10 8 6 0.5 1.0 1.5 2.0 2.5 3.0 0 41 4 input threshold voltage vs. supply voltage (c l = 0nf) max5048c toc08 rising falling supply current vs. logic inpu t voltage (v+ = 10v, c l = 0nf) max5048c toc09 logic input voltage (v) supply current (ma) 13 12 11 10 9 8 7 6 5 4 3 2 1 0.5 0.6 0.7 0.8 0.9 0.4 01 4 rising falling max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
maxim integrated 5 typical operating characteristics (continued) (c l = 1nf, t a = +25c, unless otherwise noted.) logic input voltage vs. outpu t voltage (v+ = +4v, c l = 4.7nf) max5048c toc10 20ns/div in+ 2v/div output 2v/div logic input voltage vs. outpu t voltage (v+ = +4v, c l = 10nf) max5048c toc11 20ns/div in+ 2v/div output 2v/div logic input voltage vs. outpu t voltage (v+ = +4v, c l = 4.7nf) max5048c toc12 20ns/div in+ 2v/div output 2v/div logic input voltage vs. output voltage (v+ = +4v, c l = 10nf) max5048c toc13 20ns/div in+ 2v/div output 2v/div logic input voltage vs. output voltage (v+ = +14v, c l = 4.7nf) max5048c toc14 20ns/div in+ 5v/div output 5v/div logic input voltage vs. outpu t voltage (v+ = +14v, c l = 10nf) max5048c toc15 20ns/div in+ 5v/div output 5v/div logic input voltage vs. output voltage (v+ = +14v, c l = 4.7nf) max5048c toc16 20ns/div in+ 5v/div output 5v/div logic input voltage vs. outpu t voltage (v+ = +14v, c l = 10nf) max5048c toc17 20ns/div in+ 5v/div output 5v/div max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
maxim integrated 6 pin description pin confguration functional diagram figure 1. max5048c functional block diagram pin name function 1 v+ power-supply input. bypass to gnd with a minimum of 1f low-esr ceramic capacitor. 2 p_out open-drain p-channel output. sources current for mosfet turn-on. 3 n_out open-drain n-channel output. sinks current for mosfet turn-off. 4 gnd ground 5 in- inverting logic input terminal. connect to gnd when not used. 6 in+ noninverting logic input terminal. connect to v+ when not used. max5048c top view p_out n_out 1 v+ 2 3 gnd 6 in+ 5 in- + 4 p p_out v+ n_out gnd in- in+ max5048c break- before- make control n max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
maxim integrated 7 timing diagram and test circuit figure 2. timing diagram and test circuit for in+ operation in+ v il 90% 10% v ih td-of ft f td-on tr out out c l p_out v+ v+ in+ in- max5048c in+ gnd in- n_out max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
maxim integrated 8 detailed description logic inputs the max5048c has a ttl inverting and noninverting input that gives the user greater flexibility in control - ling the mosfet. table 1 shows all the possible input combinations and the corresponding output states. undervoltage lockout (uvlo) when v+ is below the uvlo threshold, the output- stage n-channel device is on and the p-channel is off, independent of the state of the inputs. this holds the outputs low. the uvlo is typically 3.45v with 200mv typical hysteresis to avoid chattering. driver outputs the device provides two separate outputs. one is an open-drain p-channel, the other an open-drain n-channel. they have distinct current sourcing/sinking capabilities to independently control the rise and fall times of the mosfet gate. add a resistor in series with p_out/ n_out to slow the corresponding rise/fall time of the mosfet gate. applications information supply bypassing, device grounding, and placement ample supply bypassing and device grounding are extremely important because when large external capacitive loads are driven, the peak current at the v+ pin can approach 3a, while at the gnd pin the peak current can approach 7a. v+ drops and ground shifts are forms of negative feedback for inverters and, if excessive, can cause multiple switching when the inverting input is used and the input slew rate is low. the device driving the input should be referenced to the gnd pin, especially when the inverting input is used. ground shifts due to insufficient device grounding may disturb other circuits sharing the same ac ground return path. any series inductance in the v+, p_out, n_out, and/or gnd paths can cause oscillations due to the very high di/dt that results when the device is switched with any capacitive load. a minimum of 1f, low-esr ceramic capacitor is recommended, bypassing v+ to gnd and placed as close as possible to the pins. when driving very large loads (e.g., 10nf) at minimum rise time, 10f or more of parallel storage capacitance is recommended. a ground plane is highly recommended to minimize ground return resistance and series inductance. care should be taken to place the device as close as possible to the external mosfet being driven to further minimize board inductance and ac path resistance. power dissipation power dissipation of the device consists of three compo - nents, caused by the quiescent current, capacitive charge and discharge of internal nodes, and the output current (either capacitive or resistive load). the sum of these components must be kept below the maximum power- dissipation limit corresponding value. the quiescent current is 0.5ma (typ). the current required to charge and discharge the internal nodes is frequency dependent (see the typical operating characteristics ). the devices approximate power dissipation when driving a ground-referenced resistive load is: p = d x r on (max) x i load 2 where d is the fraction of the period that the device output pulls high, r on (max) is the maximum pullup on-resistance of the device with the output high, and i load is the output load current of the device. for capacitive loads, the approximate power dissipation is: p = c load x (v+) 2 x freq where c load is the capacitive load, v+ is the supply voltage, and freq is the switching frequency. pcb layout information the mosfet driver can source and sink large currents to create very fast rise and fall edges at the gate of the switching mosfet. the high di/dt can cause unaccept - able ringing if the trace lengths and impedances are not well controlled. the following pcb layout guidelines are recommended when designing with the max5048c: place at least 1f decoupling ceramic capacitor from v+ to gnd as close as possible to the device. at least one storage capacitor of 10f (min) should be located on the pcb with a low resistance path to the v+ pin of the device. table 1. truth table l = logic-low. h = logic-high. in+ in- p_out n_out l l off on l h off on h l on off h h off on max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
maxim integrated 9 there are two ac current loops formed between the device and the gate of the mosfet being driven. the mosfet looks like a large capacitance from gate to source when the gate is being pulled low. the active current loop is from n_out of the device to the mosfet gate, to the mosfet source, and to gnd of the device. when the gate of the mosfet is being pulled high, the active current loop is from p_out of the device, to the mosfet gate, to the mosfet source, to the gnd terminal of the decoupling capacitor, to the v+ terminal of the decoupling capacitor, and to the v+ terminal of the device. while the charging current loop is important, the discharging current loop is also critical. it is important to minimize the physical distance and the impedance in these ac current loops. in a multilayer pcb, the component surface layer sur - rounding the device should consist of a gnd plane containing the discharging and charging current loops. figure 3. noninverting application figure 4. boost converter figure 5. max5048c in high-power synchronous buck converter typical application circuits p_out v s v+ max5048c in+ gnd in- n_out v+ (4v to 14v) p_out v out v s v+ max5048c in+ gnd in- n_out v+ (4v to 14v) from pw m controller (boost ) p_out in+ p max5048c in- gnd v+ v+ n_out (4v to 14v) from pw m controller (buck ) p_out in+ v out max5048c in- gnd n_out max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
maxim integrated 10 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos +denotes a lead(pb)-free/rohs-compliant package. ordering information part temp range pin- package logic input top mark MAX5048CAUT+ -40c to +125c 6 sot23 ttl +acsc package type package code outline no. land pattern no. 6 sot23 u6+8 21-0058 90-0175 max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver www.maximintegrated.com
? 2015 maxim integrated products, inc. 11 revision history revision number revision date description pages changed 0 11/12 initial release 1 1/15 updated benefts and features section 1 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max5048c 7a sink/3a source current, 8ns, sot23, mosfet driver for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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